• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to a dual damascene wiring forming method suitable for forming a fine pattern, comprising the steps of depositing a diffusion barrier, an interlayer insulating film, and a first metal hard mask on a semiconductor substrate having a lower metal wiring formed in an insulating layer. ; Partially etching a predetermined thickness of the first metal hard mask using a first photoresist pattern as a mask to have an embossed trench pattern; Forming a second metal hard mask having different etching selectivity in the partially etched region of the first metal hard mask; Selectively etching the first metal hard mask to have an intaglio via hole pattern using a second photoresist pattern as a mask; Partially etching a predetermined thickness of the interlayer insulating layer into a via hole pattern using the first metal hard mask; Removing the exposed first metal hard mask and selectively etching the interlayer insulating film using the second metal hard mask to form trenches and via holes.
    公开号:KR20030000820A
    申请号:KR1020010036969
    申请日:2001-06-27
    公开日:2003-01-06
    发明作者:홍은석
    申请人:주식회사 하이닉스반도체；
    IPC主号:
    专利说明:

    Dual damascene wiring formation method {METHOD FOR FORMING DUAL-DAMASCENE INTERCONNECT STRUCTURES}
    [10] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the formation of multi-layered metal wirings, and more particularly to a method of forming dual damascene wirings suitable for forming fine patterns.
    [11] Various methods have been proposed for forming via holes and trenches in the dual damascene wiring forming method.
    [12] Typical methods include a method of forming a trench after forming a via hole and a method of forming a via hole after forming a trench.
    [13] In this method, since the photosensitive film pattern is formed on the stepped portions such as the via hole and the trench, which are previously opened, the shape defect of the photosensitive film pattern becomes a problem.
    [14] Hereinafter, a dual damascene wiring method according to the prior art will be described with reference to the accompanying drawings.
    [15] 1A to 1D are cross-sectional views for describing a dual damascene wiring method according to a first method of the related art, and FIGS. 2A to 2D are diagrams for describing a dual damascene wiring method according to a second method of the related art. It is a process cross section.
    [16] In forming the dual damascene wiring, the first conventional method is to form a trench after first forming a via hole, and the second method is to form a via hole after first forming a trench.
    [17] In the conventional method for forming dual damascene wiring according to the first method, as illustrated in FIG. 1A, the insulating layer 2 on the semiconductor substrate 1 is selectively etched to form a trench for forming lower metal wiring, and the trench A metal material is embedded and planarized in the bottom to form the lower metal wiring 3.
    [18] Subsequently, an interlayer dielectric 5 is deposited by depositing a diffusion barrier 4 on the lower metal wiring 3 and by depositing a low dielectric constant material on the diffusion barrier 4.
    [19] After the photoresist is coated on the interlayer insulating film 5, a photoresist pattern 6 having a via hole pattern is formed through an exposure and development process so that a predetermined region is exposed.
    [20] The photoresist pattern 6 may be formed thick for deep via hole etching in the interlayer insulating film 5 of a subsequent process, or may have a large etching selectivity with respect to the interlayer insulating film 5.
    [21] The interlayer insulating layer 5 is etched using a plasma dry etching method using the photoresist pattern 6 as a mask to form via holes therein.
    [22] As shown in FIG. 1B, after the photoresist pattern 6 is removed, a polymer remaining in the via hole is removed through a cleaning process.
    [23] As shown in FIG. 1C, after the photoresist film is applied on the interlayer insulating film 5, the photoresist pattern 6a having the trench pattern is formed by patterning in a negative manner so that a predetermined region is exposed.
    [24] Next, as shown in FIG. 1D, the interlayer insulating film 5 is selectively etched using the photosensitive film pattern 6a as a mask to form a trench.
    [25] At this time, in the etching process, a micro-trench (Micro-Trench) is generated inside the trench.
    [26] After the deposition of a metal material such as tungsten to a thickness sufficient to completely fill the via hole and the trench, the planarization is performed such that the upper surface of the interlayer insulating layer 5 is exposed by chemical mechanical polishing (CMP). To form a plug (not shown) and an upper metal wiring (not shown).
    [27] The conventional dual damascene wire forming method has a simple process, and has an advantage of preventing the dielectric constant of the interlayer insulating film 5 from increasing due to the diffusion barrier film 4, and thus requires deep etching to form a via hole. The thickness of the photoresist pattern 6 may be thick, or the etching selectivity of the interlayer insulating layer 5 with respect to the photoresist pattern 6 may be large.
    [28] In addition, it is difficult to remove the polymer remaining in the via hole, and the micro-trench phenomenon occurs during the trench formation.
    [29] The dual damascene wiring forming method according to the second conventional method includes the diffusion barrier film 24 on the semiconductor substrate 21 including the lower metal wiring formed in the insulating layer 22, as shown in FIG. The first interlayer insulating film 25, the etch stop layer 26, and the second interlayer insulating film 27 are sequentially deposited.
    [30] After the photoresist is coated on the second interlayer insulating layer 27, a photoresist pattern 28 having a trench pattern is formed through an exposure and development process so that a predetermined region is exposed.
    [31] As shown in FIG. 2B, the second interlayer insulating layer 27 is plasma-dried using the photoresist pattern 28 as a mask to form a trench to expose a portion of the etching stop layer 26.
    [32] As shown in FIG. 2C, after the photoresist pattern 28 having the trench pattern is removed, the photoresist layer 28 is applied to the entire surface of the photoresist layer and patterned in a negative manner so that a predetermined region is exposed to form the photoresist pattern 28a having the via hole pattern. Form.
    [33] Subsequently, as shown in FIG. 2D, the etching stop layer 26, the first interlayer insulating layer 25, and the diffusion barrier layer 24 are exposed to expose a part of the lower metal wiring by using the photoresist pattern 28a as a mask. It is selectively etched to form via holes.
    [34] Then, a metal material such as tungsten is deposited to a thickness sufficient to completely fill the via hole and the trench, and then planarized to expose the upper surface of the second interlayer insulating layer 27 by chemical mechanical polishing. Not shown) and the upper metal wiring (not shown).
    [35] The conventional dual damascene wire forming method is easy to control the etching depth and profile during the trench and via hole etching, but it is difficult to control the size of the via hole when forming the photoresist pattern for via hole etching and the interlayer insulating film due to the etch stop layer The dielectric constant of is increased.
    [36] However, the conventional dual damascene wiring formation method as described above has the following problems.
    [37] When etching the via hole and the trench by etching the interlayer insulating layer using the photoresist pattern as a mask, it is difficult to form a fine pattern due to the thickness of the photoresist pattern.
    [38] This not only makes it difficult to accurately control the size of the via hole or trench, but also generates a large amount of polymer in the etching process of the interlayer insulating film.
    [39] The present invention is to solve the problem of the dual damascene wiring method of the prior art, by forming a via hole and a trench using two metal hard masks having different etching characteristics, dual damascene capable of fine pattern formation It is an object of the present invention to provide a wiring forming method.
    [1] 1A to 1D are cross-sectional views illustrating a method for forming a dual damascene wiring according to a first method of the related art.
    [2] 2A to 2D are cross-sectional views illustrating a method for forming a dual damascene wiring according to a second conventional method.
    [3] 3A to 3H are cross-sectional views illustrating a method for forming a dual damascene wiring according to the present invention.
    [4] Explanation of symbols for the main parts of the drawings
    [5] 21 semiconductor substrate 22 insulating layer
    [6] 23: lower metal wiring 24: diffusion barrier
    [7] 25 interlayer insulating film 26 first metal hard mask
    [8] 27,27a: Photosensitive film pattern 28: Second metal hard mask
    [9] 29: trench 30: via hole
    [40] The dual damascene wiring forming method according to the present invention for achieving the above object comprises the steps of depositing a diffusion barrier film, an interlayer insulating film, a first metal hard mask on a semiconductor substrate having a lower metal wiring formed in the insulating layer; Partially etching a predetermined thickness of the first metal hard mask using a first photoresist pattern as a mask to have an embossed trench pattern; Forming a second metal hard mask having different etching selectivity in the partially etched region of the first metal hard mask; Selectively etching the first metal hard mask to have an intaglio via hole pattern using a second photoresist pattern as a mask; Partially etching a predetermined thickness of the interlayer insulating layer into a via hole pattern using the first metal hard mask; Removing the exposed first metal hard mask and selectively etching the interlayer insulating layer using the second metal hard mask to form trenches and via holes.
    [41] Hereinafter, a method of forming dual damascene wiring of the present invention will be described with reference to the accompanying drawings.
    [42] 3A to 3H are cross-sectional views illustrating a method for forming a dual damascene wiring according to the present invention.
    [43] As shown in FIG. 3A, a lower metal wiring forming trench is formed in the insulating layer 32 on the semiconductor substrate 31 in a damascene manner, and a metal material is embedded in the lower metal wiring forming trench. The metal wiring 33 is formed.
    [44] Subsequently, a silicon nitride having a low dielectric constant is deposited on the lower metal wiring 33 to form a diffusion barrier 34, and a low-k material is deposited on the diffusion barrier 34 to form an interlayer insulating film. (35) is formed.
    [45] The interlayer insulating film 35 becomes an insulating film between the lower metal wiring 33 and the upper metal wiring formed later.
    [46] In addition, a metal material is deposited on the interlayer insulating layer 35 to form a first metal hard mask 36.
    [47] Here, the first metal hard mask 36 is a material that is well etched into the plasma activated with Cl 2 + BCl 3 + N 2 gas, such as a titanium film (Ti), a titanium nitride film (TiN), and a tantalum film (Ta). And tantalum nitride film (TaN).
    [48] Then, after applying the photoresist film on the first metal hard mask 36, a first photoresist pattern 37 having an embossed trench pattern is formed through an exposure and development process so that a predetermined region is exposed.
    [49] Here, the first photoresist layer pattern 37 is formed to a minimum thickness capable of partially etching a predetermined thickness of the first metal hard mask 36.
    [50] As described above, the first photoresist pattern 37 having a thin thickness and the first metal hard mask 36 having a flat surface having no surface curvature may not only easily implement a fine pattern but also accurately implement a critical dimension of the pattern. To help.
    [51] As shown in FIG. 3B, a predetermined thickness of a region of the first metal hard mask 36 is partially removed by using the first photosensitive film pattern 37 having an embossed trench pattern as a mask.
    [52] In this case, the etching process partially etching the region of the first metal hard mask 36 which is not protected by the first photoresist pattern 37 using a plasma activated with Cl 2 + BCl 3 + N 2 gas.
    [53] This is because the first metal hard, which is a Ti or Ta based material, cannot be deposited directly on the lower interlayer insulating film 35 when tungsten, which is used as the material of the second metal hard mask 38, is deposited in a subsequent process. This is for depositing on the mask 36a.
    [54] In addition, the first metal hard mask 36a may have an embossed trench pattern due to the first photoresist pattern having an embossed trench pattern.
    [55] As shown in FIG. 3C, after removing the first photoresist layer pattern 37, tungsten is deposited on the entire surface of the first metal hard mask 36a, and the chemical mechanical polishing (CMP) method is used. The surface of the first metal hard mask 36a is flattened to form a second metal hard mask 38.
    [56] Here, the second metal hard mask 38 is formed in the form of an intaglio metal line due to the first metal hard mask 36a patterned in an embossed manner.
    [57] Therefore, the reticle used at this time may implement a damascene pattern using a general reticle instead of a forming reticle for damascene.
    [58] As shown in FIG. 3D, after the photoresist is coated on the first and second metal hard masks 36a and 38, the first metal hard mask 36a is subjected to an exposure and development process so that a predetermined region is exposed. ), A second photosensitive film pattern 37a having a negative via hole pattern is formed.
    [59] Here, the second photoresist layer pattern 37a is formed to a minimum thickness capable of etching only the first metal hard mask 36a.
    [60] Accordingly, the second photoresist film pattern 37a having a thin thickness and the first and second metal hard masks 36a and 38 having no surface curvature by flattening by chemical mechanical polishing are easy to realize a fine pattern and have a critical surface of the pattern. Can also be implemented accurately.
    [61] Thereafter, as illustrated in FIG. 3E, the first metal hard mask 36a is selectively etched using the second photoresist pattern 37a as a mask.
    [62] At this time, the etching process forms a via hole pattern by etching the first metal hard mask 36a until the interlayer insulating layer 35 is exposed using a plasma activated with Cl 2 + BCl 3 + N 2 gas.
    [63] As shown in FIG. 3F, after the second photosensitive layer pattern 37a is removed, the interlayer insulating layer may be formed using the first metal hard mask 36b and the second metal hard mask 38 having a via hole pattern as a mask. 35 is selectively etched to form a via hole pattern in the interlayer insulating layer 35a.
    [64] Here, the via hole pattern formed in the interlayer insulating layer 35a may have a high etching selectivity with respect to the first metal hard mask 36b, and C a F b + C x H y F z + Ar (a, b, x, y, z: integer) is formed by an etching process using a plasma activated with a mixed gas.
    [65] In addition, the via hole pattern is etched into a shape having excellent anisotropy and a small cross-sectional change without becoming a so-called boeing shape having a large change in the cross-sectional shape in the depth direction, and etching the interlayer insulating film 35a without any photosensitive film. Because of this, less metal polymer is generated.
    [66] As shown in FIG. 3G, the exposed area of the first metal hard mask 36b is removed using the second metal hard mask 38 as a mask.
    [67] At this time, the first metal hard mask 36b is selectively etched using a plasma activated with Cl 2 + BCl 3 + N 2 gas, and the plasma process has a low etching ratio for tungsten and an oxidizing material. The metal hard mask 38 and the interlayer insulating layer 35a are hardly etched, and only the exposed portions of the first metal hard mask 36b are removed.
    [68] 3H, the second metal hard mask 38 may be selectively etched through the interlayer insulating layer 35a etched in the via hole pattern using the second metal hard mask 38 as a mask to reach the lower metal wiring 33. Via holes and trenches are formed simultaneously.
    [69] At this time, the interlayer insulating layer 35a is etched using a plasma obtained by activating C a F b + C x H y F z + Ar (a, b, x, y, z: integer) gas, and the above etching process is performed. The second metal hard mask 38 is also removed.
    [70] Subsequently, after the first metal hard mask 36c is removed, a metal material is deposited to a thickness sufficient to completely fill the via holes and trenches, and the upper surface of the interlayer insulating layer 35b is exposed by chemical mechanical polishing. The planarization is performed to form plugs (not shown) and upper metal wirings (not shown).
    [71] The dual damascene wiring forming method of the present invention as described above has the following effects.
    [72] By reducing the thickness of the photoresist film for patterning the hard mask and patterning the photoresist on the hard mask of a perfect flat plate, a fine pattern can be realized.
    [73] This makes it easy to adjust the size of the via hole or trench and has an effect of accurately forming the critical plane.
    [74] In addition, since the etching process of the interlayer insulating film is performed in the absence of the photosensitive film, the amount of polymer generated can be reduced.
    权利要求:
    Claims (5)
    [1" claim-type="Currently amended] Depositing a diffusion barrier film, an interlayer insulating film, and a first metal hard mask on a semiconductor substrate having a lower metal wiring formed in the insulating layer;
    Partially etching a predetermined thickness of the first metal hard mask using a first photoresist pattern as a mask to have an embossed trench pattern;
    Forming a second metal hard mask having different etching selectivity in the partially etched region of the first metal hard mask;
    Selectively etching the first metal hard mask to have an intaglio via hole pattern using a second photoresist pattern as a mask;
    Partially etching a predetermined thickness of the interlayer insulating layer into a via hole pattern using the first metal hard mask;
    Removing the exposed first metal hard mask and selectively etching the interlayer insulating film using the second metal hard mask to form trenches and via holes.
    [2" claim-type="Currently amended] 2. The dual damascene of claim 1, wherein the first metal hard mask is formed of any one of a titanium film, a titanium nitride film, a tantalum film, and a tantalum nitride film, and the second metal hard mask is formed of tungsten. Wiring formation method.
    [3" claim-type="Currently amended] The method of claim 1, wherein the first metal hard mask is etched using a plasma activated with Cl 2 + BCl 3 + N 2 gas.
    [4" claim-type="Currently amended] The method of claim 1, wherein the interlayer insulating layer is etched using a plasma activated by a gas of C a F b + C x H y F z + Ar (a, b, x, y, z: integer). Dual damascene wiring formation method.
    [5" claim-type="Currently amended] The minimum thickness of claim 1, wherein the first photoresist layer pattern is formed to a minimum thickness capable of partially etching a predetermined thickness of the first metal hard mask, and the second photoresist layer pattern is a minimum thickness capable of etching only the first metal hard mask. Dual damascene wiring forming method characterized in that the formation.
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    同族专利:
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2001-06-27|Application filed by 주식회사 하이닉스반도체
    2001-06-27|Priority to KR20010036969A
    2003-01-06|Publication of KR20030000820A
    2003-06-09|Application granted
    2003-06-09|Publication of KR100386621B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR20010036969A|KR100386621B1|2001-06-27|2001-06-27|Method for forming dual-damascene interconnect structures|
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